1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
2. Description of Related Art
A typical method of packaging semiconductor chips is wafer-level packaging (WLP). The WLP method involves applying a liquid resin to a semiconductor wafer, curing the liquid resin into a sealing layer, and dividing the semiconductor wafer together with the sealing layer into small pieces (See Japanese Unexamined Patent Application Publication No. 2011-176069, Japanese Patent No. 4725638, and Japanese Patent No. 4725639). This method enables the production of small packages with substantially the same size as that of semiconductor chips.
A thermosetting liquid resin shrinks when it is cured. This causes warpage of a semiconductor wafer and semiconductor chips produced by division of the semiconductor wafer into small pieces. In particular, as the thickness of the semiconductor wafer decreases, its warpage increases.
The recent advance on reduced dimensions of mobile devices (end products) leads to an increasing demand for thinner semiconductor components to be implemented on such devices.
Further thinning of semiconductor chips according to the WLP method involving the use of a wafer should clear the following challenges:
(A1) Transfer of a thinned wafer having a reduced strength without damage.
(A2) Prevention of the warpage of a wafer: As the thickness of the Si layer decreases, the warpage of the wafer increases during processing to the extent that it can be no longer processed. For example, a robot hand cannot suck a wafer for transfer; a wafer cannot be sucked on a stage for processing or accommodated in a cassette slot; or a notch aligner centering the wafer to detect the orientation of the wafer cannot be focused on the wafer, leading to abnormal operation.
(A3) Prevention of the warpage of the structure of a chip (maintenance of uniformity or coplanarity): Individual chips from a warped wafer also warp and cause problems when implemented on devices or adversely affect their reliability.
(A4) For wafers which are vulnerable to large warpage and adversely affect reliability due to their fragile structure in the device, such as (1) those having a low-k multilayer wiring structure and (2) those having memory cells, preventing warpage is crucial to improve a yield rate and reliability.
As mentioned above, the warpage of a wafer is generally caused by shrinkage of a thermosetting resin. As the semiconductor substrate becomes thinner, the warpage increases and, in particular, more increases in the following cases:
(B1) Large chips from a wafer having a thin semiconductor substrate
(B2) The wafer has structures, such as rewiring layers, electrodes for external connections (bumps, posts, or pillars), or UBM layers functioning as electrodes for external connections. It is known from the experience that any combination of these structures with a thermosetting resin further aggravates the warpage. A direct contact of a resin film with rewiring layers, UBM layers, or bump electrodes generates a high stress, which causes warpage.
(B3) A rewiring layer on a semiconductor substrate has a large area for routing common signal wires for power supply and grounding.